Jump to: , Contents 1 2 3 4 5 An application-specific integrated circuit (abbreviated as ASIC) is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use.In Bitcoin mining hardware, ASICs were the next step of development after CPUs, GPUs and FPGAs.Capable of easily outperforming the aforementioned platforms for Bitcoin mining in both speed and efficiency, all Bitcoin mining hardware that is practical in use will make use of one or more Bitcoin (SHA256d) ASICs.Note that Bitcoin ASIC chips generally can only be used for Bitcoin mining.While there are rare exceptions - for example chips that mine both Bitcoin and Litecoin - this is often because the chip package effectively has two ASICs: one for Bitcoin and one for Litecoin.The ASIC chip of choice determines, in large part, the cost and efficiency of a given miner, as ASIC development and manufacture are very expensive processes, and the ASIC chips themselves are often the components that require the most power on a Bitcoin miner.

While there are many Bitcoin mining hardware manufacturers, some of these should be seen as systems integrators - using the ASIC chips manufactured by other parties, and combining them with other electronic components on a board to form the Bitcoin mining hardware.how to sell bitcoin legallyThe pace at which Bitcoin ASICs have been developed, for a previously non-existent market, has seen some academic interest.bitcoin-qt label addressOne paper titled "Bitcoin and The Age of Bespoke Silicon" notes: The Bitcoin and Cryptocurrency Technologies online course by Princeton University notes: A timeline overview for CoinTerra's Goldstrike 1 chip also shows this as 8 months between founding the company and shipping a product.bitcoin blockchain split

A Bitcoin ASIC's specification could be seen as having a certain hash rate (e.g.Gh/s) at a certain efficiency (e.g.While cost is another factor, this is often a relatively fixed factor as the minimum cost of a chip will be determined by the fabrication process, while the maximum cost will be determined by market forces, which are outside of post-fabrication technological control.ethereum value in gbpWhen reading the specifications for ASICs on this page is that they should be interpreted as being indicative, rather than authoritative.pagare bitcoin con paypalMany of the figures will have come from the manufacturers, who will present their technology in the best light - be that high hash rates that in practice may not be very efficient and require additional cooling, or very high efficiency at a cost of hash rate and risking being slow in the race against difficulty adjustments.bitcoin wallet data directory

Complicating the matter further is that Bitcoin ASICs can often be made to cater to both ends of the spectrum by varying the clock frequency and/or the power provided to the chip (often via a regulated voltage supply).As such, chips can not be directly compared.Two proposals have been made in the past for attempts at comparing ASICs - Gh/mm² and η-factor.Gh/mm² is a simple measure of the number of Gigahashes per second of the chip, divided by its die area (area of the the actual silicon).This measure however does not take into account the node size which affects how many logical cells can fit in a given area.As a result, η-factor was suggested at the BitcoinTalk Forums which attempts to take the node size into account, by multiplying the Gh/mm² value by the half the node size, three times.Although the merit of these approaches can be debated, ultimately these figures are not as important as the ones that detail what is required to make an ASIC work.If an ASIC requires highly stable power supply, then the power supply circuitry on a board may be more expensive than for another ASIC.

If the ASIC has a complex communications protocol, additional relatively expensive components may be required.If an ASIC's die is large, fewer (rectangular slices) can be obtained from a (circular) wafer, defects affect its design dispropotionately, and cooling solutions are generally more complex compared to smaller die chips which in turn have other overhead.Chips with a BGA design are less simple to integrate than a QFN, requiring more expensive (inspection and testing) equipment.Nevertheless, for historic purposes they are included in listings here where sufficient information is available.One other oft-mentioned number statistic for an ASIC chip is the number of cores or hashing engines that are on the chip.While this number is directly related to performance, it is not necessarily a comparitive relation.Bitmain Technologies' BM1382 calculates 63 hashes per clock cycle (Hz), while their more efficient BM1384 calculates 55 hashes per clock cycle.Similarly, while these hashes per clock cycle are spot-on for the claims regarding the number of cores, BitFury's BF756C55 is claimed to have 756 cores, but yields around 11.6 hashes per clock cycle.

This is because the reference to cores sometimes mean different things, and certain designs result in less straightforward calculation[1] Nevertheless, when a designer makes claims regarding hash rates at certain clock frequencies, one can determine if A. there is a straightforward calculation and B. if the designer is being imprecise (rounding values) or even intentionally dishonest, as the ratio between clock cycles and hash rate should remain the same.List of Bitcoin mining ASICscommits branch releases Fetching contributors GPL-3.0 C Latest commit 5cbab90 Jan 7, 2014 Updated cgminer README Permalink README.txt An Open Source FPGA Litecoin (scrypt) miner This code is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the GNU General Public License for more details./progranism/Open-Source-FPGA-Bitcoin-Miner /ckolivas/cgminer/blob/master/scrypt.c Discussion is at https://forum.litecoin.net/index.php/topic,5162.0.html Special thanks to fpgaminer for the original bitcoin mining code, teknohog for his LX150 code, also OrphanedGland, udif, TheSeven, makomk, and newMeat1 as credited on /index.php?topic=9047.0 and ngzhang for his Icarus/Lancelot boards and github.

The scrypt algorithm is implemented using on-chip FPGA RAM, so should be portable to any FPGA large enough to support 1024kBit of RAM (512kBit with interpolation, eg DE0-Nano).External RAM support could be added, but requires the relevant RAM controller for the board.Performance will be limited by RAM bandwidth.The code is proof of concept, further optimisation is required (only a small performance gain is to be expected though).Internal (pll derived) clock is only 25MHz, limited by the salsa_core.Further pipelining would increase this, but gives no performance gain since the scrypt algorithm is essentially serial.RAM is also clocked at this speed, a faster clock would help improve performance a little (and is essential for external RAM) at the expense of complexity.Multiple cores are best implemented using the 512kBit scratchpad as the slower individual throughput is more than compensated by doubling the number of cores supported.MULTICORE is now the default.

This only affects nonce handling so its safe to use with singe cores which will simply scan a more limited range (the top nibble is fixed at 0).To revert to the previous behaviour set the NOMULTICORE macro (but ONLY if using a single core).Contents -------- DE2-115-Single Single full scratchpad core, this is the simplest implementation.DE0-Nano Uses interpolation as the full scratchpad does not fit (this is the same as LOOKUP_GAP=2 in GPU).Test results ... 1.16 kHash/sec at 25Mhz (this is Fmax at 85C/Slow model) 2.09 kHash/sec at 45Mhz Fmax is 25MHz, so anything greater may not work reliably on your device.BEWARE the onboard psu regulators run HOT to VERY HOT.You may fry them!experimental New code, not all fully working.ICARUS-LX150 A Xilinx LX150 multicore port for ngzhang's Icarus/Lancelot boards.source Verilog source code.Ztex and Cairnsmore CM1 ----------------------- Ports for the Ztex 1.15y and Cairnsmore CM1 quad boards are available in the experimental folder.